The present invention relates to a framework for EDA design convergence.
FIG. 1 shows a high level view of a typical SoC design flow. In a conventional system on a chip (SoC) process, a design specification 1 is processed by an architecture/microarchitecture design optimization block 40. The result of the block 40 is a behavioral register transfer language (RTL) 150 which is received by a netlist synthesis block 50. A gate level netlist 160 is generated, from which a physical synthesis block 60 can use to generate a full chip layout. The layout can be analyzed by a full chip analysis block 70. Delay dependency updates can be provided as feedback to the architecture/microarchitecture design optimization block 40. Additionally, critical delay information can be provided to the netlist synthesis module 50. Typically, the process requires the complete design to be accomplished over multiple specialized optimization blocks 40, 50, and 60. Even a single specialized optimization is accomplished as an iterative incremental refinement (for example iterations 100 or 110 or 120) since most of these optimization problems cannot be easily formulated and solved as a pure closed-form analytical equation. Even though each optimization flow works independent of other optimization flows, the modified designs could impact the performance of other optimization flows. Thus when entire design is put together, systemic sub-optimality is discovered and many of the optimization flows may need to be re-run (for example iterations 130 or 140) with some additional constraints or modifications to cost functions. Many times these additional constraints or modifications could uncover newer issues while solving older issues. Thus design closure is a significant risk.
One risk to design closure comes from the fact that earlier optimization flows like architecture optimization block 40 is performed on more abstract design model than later optimization flows like physical design optimization block 60. Many optimization decisions made in earlier part of the design cycle may not be consistent with details included in the latter part of the flow. Such inconsistencies may mask real critical paths, causing optimization engines to focus more aggressively on lesser critical paths, leading to a situation where fixing real critical paths later is much harder, if not impossible. In fact, these poorly directed initial optimizations may have to be identified and unwound as well to eliminate false critical paths.
Another risk to design closure comes from adopting hierarchical design methods in an effort to deal with tool capacity (memory and turn-around time) limitations. These design methods avoid having to analyze/design full circuit paths end-to-end in one-go. This piece-meal approach could potentially elude design convergence as designers and tools dance between different aspects of the same circuit at different times.
Yet another risk to design closure comes from inadequate constraints being specified on optimizations. In the current design environment setting up appropriate constraints on different optimization flows is largely manual step requiring an expert knowledge. In terms of convergence rate and quality, it is desirable to set the maximum possible valid constraining conditions on the optimization flows. It is very time consuming and error prone to determine these constraints manually. The opportunity for greater automation of constraint generation exists, but the challenge lies in the fact that as design flows move from one tool to another, there is no continuity in the data model and hence necessary information may not be available in one convenient place. For example, physical synthesis may try to optimize logic placement based on number of signals they share. On the other hand, architecture optimization flow is aware of some signals that may be more likely to be activated than others and hence knows that such signals should be given greater weight than physical synthesis would normally do. In order to accomplish this, it would be necessary to set some constraints such as relative grouping of underlying hardware blocks. The AO does not know how to set placement constraints. Physical synthesis does not know the dynamic signal priority. Thus there is discontinuity in the underlying data model.